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A LOW COMPLEXITY AND LOW POWER SOC DESIGN ARCHITECTURE FOR ADAPTIVE MAI SUPPRESSION IN CDMA SYSTEMS

By Yuanbin Guo and Joseph R. Cavallaro

Abstract

In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from O(K 2 N) to O(KN). The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least 10 × saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least 4 × speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to 90%

Topics: interference cancellation, low power, CDMA, adaptive, SoC, VLSI
Year: 2009
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.4958
Provided by: CiteSeerX
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