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Floorplan and power/ground network co-synthesis for fast design convergence

By Chen-wei Liu

Abstract

As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasible to co-synthesize P/G network with floorplan. To make the co-synthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method. In this paper, we present a method for floorplan and P/G network co-synthesis based on an efficient P/G network analysis scheme and the B*-tree floorplan representation. We integrate the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology. Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence

Topics: Categories and Subject Descriptors, B.7.2 [Integrated Circuits, Design Aids General Terms, Algorithms, Experimentation, Performance Keywords, Floorplanning, Simulated Annealing, Power Integrity, IR Drop, Power/Ground Analysis
Publisher: ACM Press
Year: 2006
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.3872
Provided by: CiteSeerX
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