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Improved latency and accuracy for neural branch prediction

By Daniel A. Jiménez

Abstract

Microarchitectural prediction based on neural learning has received increasing attention in recent years. However, neural prediction remains impractical because its superior accuracy over conventional predictors is not enough to offset the cost imposed by its high latency. We present a new neural branch predictor that solves the problem from both directions: it is both more accurate and much faster than previous neural predictors. Our predictor improves accuracy by combining path and pattern history to overcome limitations inherent to previous predictors. It also has much lower latency than previous neural predictors. The result is a predictor with accuracy far superior to conventional predictors but with latency comparable to predictors from industrial designs. Our simulations show that a path-based neural predictor improves the instructions-per-cycle (IPC) rate of an aggressively clocked microarchitecture by 16 % over the original perceptron predictor. One reason for the improved accuracy is the ability of our new predictor to learn linearly inseparable branches; we show that these branches account for 50 % of all branches and almost all branch mispredictions

Topics: Categories and Subject Descriptors, C.1.1 [Processor Architectures, Single Data Stream Architectures General Terms, Performance Additional Key Words and Phrases, Branch prediction, machine learning
Year: 2005
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.1350
Provided by: CiteSeerX
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