Among the various tasks performcd by sofhvarc radios is thc reconfiguration of the error control coding algorithm to match the requirement of the radio personality. In the digital radio processor, proper assignment of tasks between DSPs and FPGAs provides perfornuncc improvements over the nsc of DSPs alone. Error control coding functions are good candidates to reside on the PPGA side of this ftinctiiinal partition. Unfortunately, good VLSI designs for codes using BCH or Reed-Solomon codes do not map well to FPGAs. Good FPGA designs must parallelizc at every opportunity, minimize timing delays through intelligcnt floor planning, and IISC each logic block LO its fullcst. We dcmonstrate thc merits of these concepts by comparing the performance of popular finite field multiplier designs
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