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Accurate Rise Time and Overshoots Estimation in RLC Interconnects



A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8 % of dynamic circuit simulations for a wide range of RLC loads. It is shown that the rise time decreases as the inductance effect increases. Also, a closed form expression for the maximum percentage overshoots is introduced that is within 5 % error of dynamic circuit simulations. The expressions introduced here are analytical and differentiable over all damping conditions. Hence, these solutions are suitable for design and optimization tools. 1

Year: 2009
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