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WA 17.6: A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation

By Gu-yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos and Mark Horowitz

Abstract

Adaptive power supply regulation reduces power dissipation in DSP and microprocessor cores [1,2]. A technique extends this concept to a high-performance parallel input/output (I/O) interface. An inverter, used as the basic delay element in the core of a dualloop delay-locked loop (DLL), has delay controlled by the supply voltage [3]. This control voltage is replicated by a high-efficiency switching supply to power the rest of the interface and to maximize energy-efficient operation. Figure 17.6.1 presents a detailed diagram of the dual-loop DLL and an adaptive power supply regulator. The core loop locks the delay through the delay line to half a reference clock period, which is equal to the TX_clk period, by adjusting its supply voltage [3]. A unity gain amplifier buffers the charge pump voltage to drive the delay-line, and an efficient switching regulator replicates this voltage to the rest of the system. To align the on-chip receiver clocks with th

Year: 2009
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.9342
Provided by: CiteSeerX
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