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Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits

By Yehea I. Ismail and Eby G. Friedman

Abstract

A closed-form expression for the propagation delay of a CMOS gate driving a distributed line is introduced that is within 5 % of dynamic circuit simulations for a wide range of loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed line can be over 35 % for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in interconnect. Closed-form solutions are presented for inserting repeaters into lines that are highly accurate with respect to numerical solutions. models can create errors of up to 30 % in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the and models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale. Index Terms—CMOS, high-performance, high-speed interconnect, propagation delay, VLSI

Year: 2000
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.9284
Provided by: CiteSeerX
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