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An Integrated Approach to Reducing Power Dissipation

By Jayaprakash Pisharath

Abstract

In recent years, both performance and power have become key factors in efficient memory design. In this paper, we propose a systematic approach to reduce the energy consumption of the entire memory hierarchy. We first evaluate an existing poweraware memory system where memory modules can exist in different power modes, and then propose on-chip memory module buffers, called Energy-Saver Buffers (ESB), which reside inbetween the L2 cache and main memory. ESBs reduce the additional overhead incurred due to frequent resynchronization of the memory modules in a low-power state. An additional improvement is attained by using a model that dynamically resizes the active cache based on the varying needs of a program. Our experimental results demonstrate that an integrated approach can reduce the energy-delay product by as much as 50 % when compared to a traditional non power-aware memory hierarchy. Categories and Subject Descriptors C.4 [Performance of Systems] – design studies, measurement techniques, performance attributes; B.3.2 [Memory Structures]: Design Styles – cache memories, primary memory; B.3.3 [Memor

Topics: Structures, Performance Analysis and Design Aids – simulation General Terms Algorithms, Design, Measurement, Performance Keywords Dynamic Cache, energy-delay product, Energy-Saver Buffers (ESB, integrated approach, power, RDRAM
Year: 2002
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.8819
Provided by: CiteSeerX
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