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Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories

By et al. Daniel R. Blum

Abstract

We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing incidence particle strikes, which produce disruptions with the widest possible spatial separation. Advantages with respect to size, complexity, and MBU tolerance are realized when this approach is compared to existing solutions

Year: 2007
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.8774
Provided by: CiteSeerX
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