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Development of an Architecture for an Image Compression Processor

By  and Derek B. Noonburg and Derek B. Noonburg

Abstract

1This materiaJ is based upon work supported under a National Science Foundation Graduate Fellowship. The design of an application-specific parallel architecture implementing a new image compression Mgorithm is described. This algorithm, developed by Jos ~ Moura and Nikhil BMram, achieves a higher compression ratio than the JPEG algorithm for a given image quality. The goal of this project is to design a processor which can compress 256 × 256 8-bit monochrome images at a rate of 30 frames per second. The program is optimized for digital computer execution through the use of sparse matrices and fixed point arithmetic. The code is used as the starting point for the architecture design, which is done using a synthesis approach, focusing on exploitation of fine-grain parallelism. A VLIW architecture is chosen, and a specific processor configuration is determined. Board-level and custom VLSI implementations are proposed, and their performance evaluated. It is shown that a frame rate of 30 frames per second could be achieved with a VLSI implementation

Year: 1992
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.8058
Provided by: CiteSeerX
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