We propose an algorithm for area optimisation of sequentialcircuits through redundancy removal. The algorithm finds compatible redundancies by implying values over nets in thecircuit. The potentially exponential cost of state space traversal is avoided and the redundancies found can all be removedat once. The optimised circuit is a safe delayed replacement of the original circuit. The algorithm computes a set of compati-ble sequential redundancies and simplifies the circuit by propagating them through the circuit. We demonstrate the efficacyof the algorithm even for large circuits through experimental results on benchmark circuits
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