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An 8 GHz Ultra Wideband Transceiver Testbed

By  and Deepak Agarwal and Deepak Agarwal


Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are of-ten limited by the speed of the underlying processors and FPGAs. This thesis presents the digital design for an impulse-based ultra wideband communication system capa-ble of supporting raw data rates of up to 100 MB/s. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commer-cially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non real-time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The overall objective is to demonstrate a testbed that will al-low researchers to evaluate different UWB modulation, multiple access, and coding schemes. As proof-of-concept, a scaled down prototype receiver which utilized 2 ADC

Topics: ultra-wideband, software radio, FPGA, high-speed datapath
Year: 2005
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
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