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Testing a High{Speed Data Path The Design of the RSA Crypto Chip

By Wolfgang Mayerwieser, Karl C. Posch, Reinhard Posch and Volker Schindler


Abstract High speed devices for public key cryptography are of emerging interest. For this reason, the RSA crypto chip was designed. It is an architecture capable of performing fast RSA encryption and other cryptographic algorithms based on modulo multiplication. Besides the modulo multiplication algorithm called FastMM, the reasons for its high computation speed are the As Parallel As Possible (APAP) architecture, as well as the high operation frequency. The RSA crypto chip also contains on{chip RAM and a special{purpose control logic, enabling special features like encrypted key loading. However, this control mechanism in uences to some extend testability of the MM data path which is the heart of the chip. For this reason, the RSA crypto chip has been designed to be able to evaluate the behaviour of the pure MM data path. In the following, we describe the strategies used with the RSA crypto chip for testing the MM data path under realistical conditions. In this context, analyzing control signal ow turns out to be the key action. This work has been sponsored aspart of the project Nr. P9384PHY \Sichere Kommunikation bei hohen Geschwindigkeiten " by the Austrian Science Foundation. Key Words: high speed multipliers, hardware algorithms, design for testability, publi

Topics: key
Year: 2009
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
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