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A Cost-Effective Test Flow for Homogeneous Network-on-Chip

By Re M. Amory, Eduardo W. Brião, Érika F. Cota, Marcelo S. Lubaszewski and O G. Moraes

Abstract

Network-on-Chip (NoC) [2] has recently emerged as an alternative communication architecture for complex system chips. Different aspects regarding NoC design have been studied in the literature. In a NoC-based system

Year: 2009
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.4793
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