Skip to main content
Article thumbnail
Location of Repository

A Cost-Effective Test Flow for Homogeneous Network-on-Chip

By Re M. Amory, Eduardo W. Brião, Érika F. Cota, Marcelo S. Lubaszewski and O G. Moraes


Network-on-Chip (NoC) [2] has recently emerged as an alternative communication architecture for complex system chips. Different aspects regarding NoC design have been studied in the literature. In a NoC-based system

Year: 2009
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • (external link)
  • (external link)
  • Suggested articles

    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.