Skip to main content
Article thumbnail
Location of Repository

By 

Abstract

Designing clock distribution for a WCDMA transceiver system Abstract- Clock distribution devices create and distribute multiple copies of a master clock to a variety of integrated circuits (ICs). These devices have single-ended or differential clock inputs and provide multiple outputs (single ended or differential), which are typically divided and delayed versions of the input clock. Low-phase-noise Crystal Oscillators (XOs) are commonly used to drive clock distribution devices. The sinusoidal input signal to a clock distribution device is converted to a number of square wave outputs. Statistical variations of the input reference clock and clock signal processing causes clock jitter, so a Phase Locked Loop (PLL) is often included to improve the jitter of the output clock. I

Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.2583
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.wcl.ee.upatras.gr/c... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.