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A Compile-Time Partitioning Strategy for Non-Rectangular Loop Nests

By Rizos Sakellariou

Abstract

This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop. The minimisation of load imbalance, on the basis of symbolic cost estimates, is considered the main objective; however, options which may increase other sources of overhead are avoided. Experimental results on a virtual shared memory computer are also presented

Publisher: IEEE Computer Society Press
Year: 1997
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.1874
Provided by: CiteSeerX
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