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Recharged Comparator and Multiple-Valued N-ary Frequency Divider

By René Jensen, Henning Gundersen, Johannes G. Lomsdalen and Yngvar Berg

Abstract

Abstract — This paper will present work on a recharged comparator using Semi Floating-Gate (SFG) MOS devices. The output voltage of a basic SFG MOS Comparator circuit is normally interleaved with a recharge voltage. This prohibit control of passgates, which requires binary control signals. An output buffer is introduced to allow the control of pass-gates and multiplexers (MUXs) beyond a single recharge clock period. The recharged comparator is utilized as reset logic in a recharged multiplevalued (MV) n-ary frequency divider (FDIV). The MV FDIV reduces the number of transistors required for a configurable frequency division of modulus between two and eight. This makes it applicable as bit-counter and symbol clock generator in recharged configurable serial D/A converters. Simulation data is obtained using AMS 0.35µm process parameters c35b4. Index Terms — CMOS frequency divider circuits, Multiplevalued logic circuits, Switched capacitor circuits, Semi floatinggate circuits. I.

Publisher: 2009-04-26
Year: 2006
OAI identifier: oai:CiteSeerX.psu:10.1.1.134.1091
Provided by: CiteSeerX
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