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Architecture-Specific Packing for Virtex-5 FPGAs

By Taneem Ahmed, Paul D. Kundarewich, Jason H. Anderson, Brad L. Taylor and Rajat Aggarwal

Abstract

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA – the Xilinx R○ Virtex TM-5 FPGA. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs can implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output is associated with slower speed, and therefore, must be used judiciously. We present placementbased techniques for dual-output LUT packing that lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance

Topics: B.7 [Integrated Circuits, Design Aids General Terms Design, Algorithms Keywords Field-programmable gate arrays, FPGAs, optimization, packing, placement
Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.133.98
Provided by: CiteSeerX
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