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AN INHERENTLY LINEAR CMOS MULTIPLIER

By Ying Dong, Sumit Bagga and Wouter A. Serdijn

Abstract

This paper presents a linear multiplier that can be fully implemented in CMOS technology. The circuit implements the function of mathematical multiplication for the two input signals. Since this multiplier is not a conventional mixer, some unconventional methods were use, such as, to realize the function of multiplication, a translinear loop is implemented, which is based on the exponential relation of a PN-diode in CMOS technology, while the other CMOS transistors working in strong inversion only provide gain. The targeted IC process was IBM’s 0.18 µm BiCMOS SiGe. The multiplier works up to 10 GHz and can be used for high frequency applications such as ultra-wideband autocorrelation receivers

Topics: translinear loop, exponential relation, linearity, high frequency, linear multiplier, UWB, CMOS
Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.133.9269
Provided by: CiteSeerX
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