Abstract-- This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Details are given on CHDStd-based hierarchy mechanisms and processes required to support Forward Timing-Driven Hierarchical Design capabilities needed for chip design using 0.25u- 0.18u technologies and beyond. These capabilities solve some of the key challenges identified by the semiconductor industry’s Design Productivity Crisis. This paper identifies the role of hierarchy for handling difficult chip design information issues and for large complex chip design. I
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