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Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support

By A Marongiu, A Capotondi and L Benini


Embedded manycore architectures are often organized as fabrics of tightly-coupled shared memory clusters. A hierarchical interconnection system is used with a crossbar-like medium inside each cluster and a network-on-chip (NoC) at the global level which make memory operations nonuniform (NUMA). Due to NUMA, regular applications typically employed in the embedded domain (e.g., image processing, computer vision, etc.) ultimately behave as irregular workloads if a flat memory system is assumed at the program level. Nested parallelism represents a powerful programming abstraction for these architectures, provided that (i) streamlined middleware support is available, whose overhead does not dominate the run-time of fine-grained applications; (ii) a mechanism to control thread binding at the cluster-level is supported. We present a lightweight runtime layer for nested parallelism on cluster-based embedded manycores, integrating our primitives in the OpenMP runtime system, and implementing a new directive to control NUMA-aware nested parallelism mapping. We explore on a set of real application use cases how NUMA makes regular parallel workloads behave as irregular, and how our approach allows to control such effects and achieve up to 28 7 speedup versus flat parallelism

Topics: Manycores, Nested parallelism, OpenMP, Theoretical Computer Science, Software, Hardware and Architecture, Computer Networks and Communications, Computer Graphics and Computer-Aided Design, Artificial Intelligence
Publisher: 'Elsevier BV'
Year: 2016
DOI identifier: 10.1016/j.parco.2016.02.002
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