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Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

By Phatrapornnant. T. and Michael J. Pont

Abstract

We have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study

Year: 2006
DOI identifier: 10.1109/TC.2006.29
OAI identifier: oai:lra.le.ac.uk:2381/1965
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