This paper was delivered at the Proceedings of the ASME 2007 International Design Engineering Technical Conferences & Computers and Information in Engineering Conference (IDETC/CIE 2007), September 4-7, 2007.As embedded designs become more widespread and complex they tend to use more modern processors. Such processors will often include features (such as pipelines, caches, and branch predictors) which help to improve performance. While such performance improvements are welcome, they come at the price of predictability. More specifically, the use of advanced processor hardware makes it difficult to predict the worst-case execution time (WCET) of tasks. As part of an\ud effort to address these problems, Puschner and Burns (Proc. 7th IEEE International Workshop on Object-Oriented Real-\ud Time Dependable Systems, Jan. 2002) proposed the “single path programming paradigm”. As its name implies program code written according to this paradigm has only one\ud execution path: this helps to ensure a constant execution time. Yet there are two problems with the techniques described by\ud Puschner and Burns: (i) they are applicable only to hardware which supports “conditional move” or similar instructions;(ii) their balancing approach increases power consumption. In the present paper, we begin to address both of these problems with a set of novel code-balancing techniques. The\ud effectiveness of these new techniques is explored by means of an empirical study
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