Article thumbnail
Location of Repository

Quasi-static capacitance measurements in pseudo-MOSFET configuration for D<inf>it</inf> extraction in SOI wafers

By L. Pirro, I. Ionica, X. Mescot, S. Cristoloveanu, G. Ghibaudo and L. Faraone


session posterInternational audienceWe investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density

Topics: SOI, quasi-static, pseudo-MOSFET, interface trap density, capacitance measurement, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Publisher: 'Institute of Electrical and Electronics Engineers (IEEE)'
Year: 2015
DOI identifier: 10.1109/ULIS.2015.7063820
OAI identifier: oai:HAL:hal-02004087v1
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • https://hal.archives-ouvertes.... (external link)
  • Suggested articles

    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.