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An Analysis of Memory Access Complexity for HEVC Decoder

By ?????????

Abstract

HEVC??? JCT-VC??? ?????? ????????? ?????? ????????? ?????? ????????????. HEVC??? H.264/AVC??? ?????? ??? 2?????? ????????? ??????????????? ????????????. HEVC ????????? ???????????? ??? ????????? UHD??? ???????????? ??????????????? ???????????? ????????? ?????????, HEVC??? UHD??? ???????????? ??????????????? ?????? ????????? ????????? ????????????. ????????? ???????????? ???????????? ???????????? ?????? ?????? ????????? ????????? ??????????????? ????????? ????????? ???????????? ??????????????? ????????? ????????? ??? ?????? ?????? ??????????????? ????????????. ????????? ??????????????? ???????????? ????????? ??? ????????? HEVC ??????????????? ????????? ?????? ???????????? ????????????. ????????? ?????? ???????????? ??????????????? ?????????????????? ???????????? ??????????????? HEVC ??????????????? ????????? ???????????? ???????????????. ?????? ????????? HEVC ??????????????? ?????????????????? ???????????? HEVC ??????????????? ????????? ????????? ????????? ????????????. ????????????, ??????????????? ??????????????? 6.9~40.5GB/s??? DRAM ????????? ?????????. ?????? ??????????????? ????????? ???????????? ??????????????? 2.4GB/s??? DRAM ???????????? ???????????? ????????? ????????????.HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth

Topics: HEVC, decoder, complexity, memory access, DRAM bandwidth
Publisher: ?????????????????????, 2014.
Year: 2014
DOI identifier: 10.5573/ieie.2014.51.5.114
OAI identifier: oai:repository.hanyang.ac.kr:20.500.11754/46272
Provided by: HANYANG Repository
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