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A notation for designing restoring logic circuitry in CMOS

By M. Rem and C.A. Mead

Abstract

A program notation is introduced together with a technique for translating programs in that notation into transistor diagrams for CMOS integrated circuits. A number of restrictions are imposed on the programs ensuring every circuit thus obtained to be restoring. The program notation caters to hierarchical design. It is shown how the observance of the restrictions can be checked for each level of the hierarchy separately. The techniques discussed in this paper may be viewed as a modest step towards silicon compilation

Year: 1982
DOI identifier: 10.1016/s0026-2692(82)80130-4
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Provided by: NARCIS
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