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An Area-Optimized Chip of Ant Colony Algorithm Design in Hardware Platform Using the Address-Based Method

By E. Shafigh Fard, K. Monfaredi and M. H. Nadimi

Abstract

The ant colony algorithm is a nature-inspired algorithm highly used for solving many complex problems and finding optimal solutions; however, the algorithm has a major flaw and that is the vast amount of calculations and if the proper correction algorithm and architectural design are not provided, it will lead to the increasing use of hardware platform due to the high volume of operations; and perhaps at higher scales, it causes the chip area not to work because of the high number of problems; hence, the purpose of this paper is to save the hardware platform as far as possible and use it optimally through providing a particular algorithm running on a reconfigurable chip driven by the address-based method, so that the comparison of synthesis operations with the similar works shows significant improvements as much as 1/3 times greater than the other similar hardware methods.DOI:http://dx.doi.org/10.11591/ijece.v4i6.692

Topics: , ant colony, reconfigurable chip, chip area
Publisher: Institute of Advanced Engineering and Science
Year: 2014
DOI identifier: 10.11591/ijece.v4i6.6923
OAI identifier: oai:ojs.www.iaescore.com:article/5536
Provided by: IAES journal
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