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Conditional termination check min-sum algorithm for efficient LDPC decoders

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Abstract

Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.This research was supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2015-H8501-15-1005) supervised by the IITP (Institute for Information & communications Technology Promotion)

Topics: low-power LDPC decoder, min-sum algorithm
Publisher: IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Year: 2015
DOI identifier: 10.1587/elex.12.20150738
OAI identifier: oai:repository.hanyang.ac.kr:20.500.11754/28959
Provided by: HANYANG Repository
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