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A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip

By Neil Bergmann, Peter Waldeck and John Williams

Abstract

The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialised data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multi-processing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented

Topics: reconfigurable system-on-chip, real-time, esgweb-research-egret, custom hardware processor architecture, 280304 Operating Systems, 289999 Other Information, Computing and Communication Sciences, 290903 Other Electronic Engineering, 291605 Processor Architectures, E1
Publisher: IEEE Computer Society
Year: 2003
DOI identifier: 10.1109/IWSOC.2003.1213017
OAI identifier: oai:espace.library.uq.edu.au:UQ:10722

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