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A parallel convolutional coder including embedded puncturing with application to consumer devices

By R. S. Sherratt


As consumers demand more functionality) from their electronic devices and manufacturers supply the demand then electrical power and clock requirements tend to increase, however reassessing system architecture can fortunately lead to suitable counter reductions. To maintain low clock rates and therefore reduce electrical power, this paper presents a parallel convolutional coder for the transmit side in many wireless consumer devices. The coder accepts a parallel data input and directly computes punctured convolutional codes without the need for a separate puncturing operation while the coded bits are available at the output of the coder in a parallel fashion. Also as the computation is in parallel then the coder can be clocked at 7 times slower than the conventional shift-register based convolutional coder (using DVB 7/8 rate). The presented coder is directly relevant to the design of modern low-power consumer device

Year: 2008
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  1. (2007). ETSI EN 300 744, “Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television”,V1.5.1 (2004-06) [2] Standard
  2. (1971). Nonsystematic Convolutional Codes for Sequential Decoding in Space Applications”,
  3. (2003). Parallel Punctured Convolutional Coder”,
  4. (2006). Sherratt is a senior member of the IEEE, IEEE Consumer Electronics Society and currently Vice President (Conferences) of the IEEE Consumer Electronics Society, member of the Society AdCom (2003-2008), Society awards chair

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