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8-bit AES Implementation in FPGA by Multiplexing 32-bit AES Operation

By Chi-Jeng Chang

Abstract

[[abstract]]8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction- Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.

Topics: [[classification]]53
Year: 2013
OAI identifier: oai:ir.lib.ntnu.edu.tw:309250000Q/126348
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