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High Throughput 32-bit AES Implementation in FPGA

By Chi-Jeng Chang

Abstract

[[abstract]]Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.

Topics: [[classification]]53
Year: 2013
OAI identifier: oai:ir.lib.ntnu.edu.tw:309250000Q/126345
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