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Path Specific Register Design to Reduce Standby Power Consumption

By Emre Salman and Qi Qi

Abstract

A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current

Topics: leakage current, low leakage register design, power consumption, static power, timing constraints, timing paths, Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Technology, T, DOAJ:Electrical and Nuclear Engineering, DOAJ:Technology and Engineering, Applications of electric power, TK4001-4102
Publisher: MDPI AG
Year: 2011
DOI identifier: 10.3390/jlpea1010131
OAI identifier: oai:doaj.org/article:136c450509334db3a0176a4ca461b6ee
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