This paper addresses the optimization of cell placement step in VLSI circuit design . A novel hybrid algorithm is proposed for performance and low power driven VLSI standard cell placement. The above problem is of multiobjective nature since three possibly conflicting objectives are considered to be optimized subject to the constraint of layout width. These objectives are power dissipation, timing performance, and interconnect wire length. It is well known that optimizing cell placement for even a single objective namely total wire length is a hard problem to solve. Due to imprecise nature of objective values, fuzzy logic is incorporated in the design of aggregating function. The above technique is applied to the placement of ISCAS-89 benchmark circuits and the results are compared with those obtained from individual application of GA and TS on this problem
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.