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Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power gating technique

By Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami and Hideharu Amano

Abstract

One of the benefits of coarse grained dynamically re-configurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. How-ever, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to re-duce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by ap-plying PG for ALUs and SMUs in PEs individually, 48 % of leakage power can be reduced with 9.0 % of area overhead. 1

Year: 2008
DOI identifier: 10.1109/fpt.2008.4762410
OAI identifier: oai:CiteSeerX.psu:10.1.1.976.2653
Provided by: CiteSeerX
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