Can Stochastic Modelling and Analysis of Multistage Interconnection Networks Lead to Efficient Usage of Redundancy for Fault-Tolerant Design?

Abstract

The rapid growth in device density achieved by VLSI technology over the past decade had the attention of researchers centered around the design of array processors. The systolic arrays had been designed for a wide variety of applications, and consequently formal strategies for mapping algorithms onto processor arrays wer

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oai:CiteSeerX.psu:10.1.1.922.2405Last time updated on 11/1/2017

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