Can Stochastic Modelling and Analysis of Multistage Interconnection Networks Lead to Efficient Usage of Redundancy for Fault-Tolerant Design?


The rapid growth in device density achieved by VLSI technology over the past decade had the attention of researchers centered around the design of array processors. The systolic arrays had been designed for a wide variety of applications, and consequently formal strategies for mapping algorithms onto processor arrays wer

Similar works

Full text

oai:CiteSeerX.psu: time updated on 11/1/2017

This paper was published in CiteSeerX.

Having an issue?

Is data on this page outdated, violates copyrights or anything else? Report the problem now and we will take corresponding actions after reviewing your request.