A Low-Power Area-Efficient Dynamic Circuit Using Conditionally Charging Pattern with Embedded Latching Capability

Abstract

Abstract — High speed and small area are the main advantages of the dynamic logic for digital circuits. Power consumption of this logic family is the main drawback. In this paper a new method for reducing the power consumption of dynamic circuits is presented. The proposed technique is especially suitable for large fan-in gates where the dynamic node discharges very frequently. These kinds of gates are widely used in high performance applications like microprocessors. The proposed method is used in an 8-input NOR gate and an 8-input OR gate. The power-delay product of these gates is reduced by 46.7 % and 35.15%, respectively in the 90nm CMOS technology, compared to their conventional dynamic counterparts. Meanwhile, we show that an inherent data latching capability exists in the proposed circuit that can result in reduced silicon area in pipelined structures

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oai:CiteSeerX.psu:10.1.1.906.2880Last time updated on 11/1/2017

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