The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache banks interconnected through a packet-based Network-on-Chip (NoC) communication fabric. Thus, the NoC plays a crit-ical role in optimizing the performance and power consump-tion of such non-uniform cache-based multicore architectures. While almost all prior NoC studies have focused on the de-sign of router microarchitectures for achieving this goal, in this paper, we explore the role of data compression on NoC performance and energy behavior. In this context, we examine two different configurations that explore combinations of stor-age and communication compression: (1) Cache Compression (CC) and (2) Compression in the NIC (NC). We also address techniques to hide the decompression latency by overlapping with NoC communication latency. Our simulation results with a diverse set of scientific and commercial benchmark traces reveal that CC can provide up to 33 % reduction in network latency and up to 23 % power savings. Even in the case of NC – where the data is compressed only when passing through the NoC fabric of the NUCA architecture and stored uncom-pressed – performance and power savings of up to 32 % and 21%, respectively, can be obtained. These performance bene-fits in the interconnect translate up to 17 % reduction in CPI. These benefits are orthogonal to any router architecture and make a strong case for utilizing compression for optimizing the performance and power envelope of NoC architectures. In ad-dition, the study demonstrates the criticality of designing faster routers in shaping the performance behavior. 1
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