No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder

Abstract

Abstract—The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a.18μm process show the new architecture saves more than 84 % of the power dissipated compare with a synchronised SMU design using a low power logic family and 30 % compared with a handshaking asynchronous design. I