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Semi-digital PLL architecture for ultra low bandwidth applications

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Abstract

Graduation date: 2013Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on a single die, mandating external components on the board. In order to maintain low loop bandwidth the designer is often forced to choose very low values of charge pump current which can lead to reliability issues.\ud In this work, a semi-digital architecture for very low bandwidth monolithic PLLs is proposed. This architecture eliminates large components in traditional charge-pump PLL, thus allowing the realization of on-chip low bandwidth PLLs. A 2x2mm PLL is\ud realized in 180nm CMOS with 75mHz bandwidth consuming 400μW power from 1.8V supply. The prototype PLL locks to an input clock of 1Hz and generates 20kHz output clock with a measured peak-to-peak jitter of 100ns

Topics: PLL, low bandwidth, active damping, semi-digital, 1PPS
Year: 2013
OAI identifier: oai:ir.library.oregonstate.edu:1957/37710
Provided by: ScholarsArchive@OSU

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