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A subranging analog to digital converter using four bit pipepline



Graduation date: 1993This thesis presents the design of a 10 bit Analog to\ud Digital Converter which consists of a 6 bit flash followed\ud by a 4 bit pipeline architecture. The total system is\ud described and the 4 bit pipeline is implemented on a bipolar\ud process.\ud The objective of this research is to provide an\ud alternative approach to high speed ADC designs and to\ud implement a pipeline ADC which samples at greater speeds\ud than those achieved with presently existing CMOS pipeline\ud designs.\ud This paper presents the complete architecture, the cell\ud design and simulated performance for each block in the\ud pipeline, and the measured results for the four bit pipeline\ud implementation

Year: 1993
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Provided by: ScholarsArchive@OSU
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