Graduation date: 1999The precise measurement of a capacitance difference or ratio in a digital form is\ud very important for capacitive sensors, for CMOS process characterization as well as for the\ud realization of precise switched-capacitor data converters, amplifiers and other circuits\ud utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor\ud ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor\ud capacitors into the modulator. Several single-ended circuits are introduced, and the\ud correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal\ud effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation\ud are also introduced and discussed. A fully-differential implementation is also described and\ud various common-mode feedback schemes are discussed and analyzed. Simulation and\ud experimental results show that these circuits can provide extremely accurate results even in\ud the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and\ud noise, and clock-feedthrough effect from the switches.\ud To verify the effectiveness of the circuits and simulations, two prototype chips containing\ud a single-ended realization and a fully-differential one were designed and fabricated\ud in a 1.2 μm CMOS technology. Two off-chip mica capacitors were used in the test circuits,\ud and the measured results show that very accurate results can be obtained using these circuit\ud techniques even with off-chip noise coupling and large parasitic capacitances
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