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Power estimation of superscalar microprocessor using VHDL model



Graduation date: 2000Power optimization becomes more and more important due to the design\ud cost and reliability. Sometimes high power consumption means expensive package\ud cost and low reliability. The first step in optimizing power consumption is\ud determining where power is consumed within a processor. While system-level code\ud tracing and bit transition calculation are not enough to estimate the power\ud distribution, transistor-level HSPICE simulation to model a microprocessor is too\ud complex and time-consuming.\ud In our research, a VHDL model with enhanced signal tracing function will\ud be developed based on the existing VHDL behavior model. The power\ud consumption of superscalar microprocessor in terms of switching activity and\ud capacitance will be carefully studied. Two factors served as the basis for study:\ud accessibility and importance for power calculations. A brief examination of the\ud datapath suggests that the register file, the instruction cache and data cache are\ud some of the major contributors to power usage. It was therefore decided to track the\ud input and output bit transitions to these modules. These transitions are counted along with the number of accesses to each of the modules.\ud In order to gather all of this data, the original VHDL model simulator has been enhanced. As instructions pass through the CPU, additional code is required to track and record the necessary information. For each individual instruction in the ISA, various information is recorded based on the elements in the processor that the instruction affects. For instance, if the simulator is about to execute a load instruction, the instruction uses the programmer counter, the instruction bus, data bus, the address bus, the ALU (adder) and the register file. The information being recorded for each of these elements must be updated to reflect the execution of that particular load instruction.\ud Also, the inside circuit of each module, i.e. register file, instruction cache and data cache and the 6-transistor memory cell layout considering the 0.25μm CMOS technology will be studied in order to extract the capacitance. We do not need very accurate, absolute power estimation, therefore, we will try to keep the model simple

Year: 1999
OAI identifier: oai:ir.library.oregonstate.edu:1957/33296
Provided by: ScholarsArchive@OSU

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